Mirafra has provided services in complex Software Development, Validation and creation of Regression Environments. With its excellent expertise in compilers, algorithms & data structures Mirafra has designed complex software and verification environments that are efficient, modular, and scalable.

Mirafra has leveraged its vast experience in software development and software lifecycle management to provide high-quality software validation services.

Mirafra has completed five years of operation in April 2009. Mirafra has also entered into the fifth year of engagement with a satisfied customer. It has complete ownership of software front-end comprising of, but not limited to, HDL design analysis and elaboration (with integration to a 3rd Party Tool) for the customer - a leader in emulation solutions for hardware verification and hardware-software co-verification.

1. Synthesis of System Verilog Assertions to RTL

The Customer: Customer is a leader in emulation solutions for hardware verification and hardware-software co-verification. Its solutions are used by most of the leading semiconductor companies to verify their SOC's.

 The Application: It's a HDL compiler for hardware emulation & hardware-software co-simulation.

Mirafra's responsibility:

• Study of various methodologies/algorithms to implement the SVA solution. Implementation of the most optimal NFA (Non-Deterministic Finite Automata) based algorithm to provide the final solution by converting the SVA to finite state machines.
• Support for mostly all the SVA constructs as listed in the IEEE Std 1800-2005 LRM provided.
• FSDB Dump & text output (in post-processing mode) support for SVA is also provided.
• Complete validation done in-house and an exhaustive test suite built for the same.
• Validation of solution done using SVA libraries available in public domain from Synopsys/Cadence/Mentor Graphics.

Engagement Model: A Team of 11 people for more than 4 years (on going) in ODC with T & M.

2. System Verilog support using 3rd party front-end

The Customer: Our customer is a leader in emulation solutions for hardware verification and hardware-software co-verification. Its solutions are used by most of the leading semiconductor companies to verify their SOC's.

The Application: It's an HDL compiler for hardware emulation & hardware-software co-simulation.

Mirafra's responsibility:

• Enhanced the entire compiler flow (frontend to backend) to support all SV constructs as listed in the IEEE Std 1800-2005 LRM.
• Concentrated effort to extend the static elaboration stage to take care of all new SV constructs such as type parameters, generic interfaces, hierarchical references through aggregate objects, etc.
• Integration with a 3rd party SV front-end (Cheetah) and close interaction with the vendor to improve the quality of the same to meet customer's highest quality standards.
• Complete validation done in-house and an exhaustive test suite built for the same.
• Solution also validated using a 3rd party SV test suite.

Engagement Model: A Team of 11 people for more than 4 years (on going) in ODC with T & M.

3. Integration with 3rd party System Verilog synthesis tool

The Customer: Customer is a leader in emulation solutions for hardware verification and hardware-software co-verification. Its solutions are used by most of the leading semiconductor companies to verify their SOC's.

The Application: It's an HDL compiler for hardware emulation & hardware-software co-simulation.

Mirafra's responsibility:

• Tool's flow was integrated with a 3rd party SV synthesizer (Concorde) to provide support for sv in DUT that could be successfully mapped on to hardware.
• Native support provided: synthesized netlist converted to existing object model and in-place replacement to avoid additional dump and re-parse overheads.
• Provided support for DUMP and trace.
• Complete solution validated using a 3rd party SV test suite. Flow also validated using the entire existing v2k test suite.

Engagement Model: A Team of 11 people for more than 4 years (on going) in ODC with T & M.

4. Mixed-HDL (Verilog + VHDL + SV) support using 3rd party front-end

The Customer: Customer is a leader in emulation solutions for hardware verification and hardware-software co-verification. Its solutions are used by most of the leading semiconductor companies to verify their SOC's.

The Application: It's an HDL compiler for hardware emulation & hardware-software co-simulation.

Mirafra's responsibility:

• Integration with a 3rd party front-end (MVV) to provide support for the Mixed Language Designs: Verilog + VHDL + System Verilog. All design constructs are supported.
• Three step flow implemented: analyze (verilog analyzer, vhdl analyzer), elaboration and simulation. Mostly all standard switches (for the 3-step flow) are supported.
• Support for hierarchical references across language boundaries.
• Complete validation done in-house and an exhaustive test suite built for the same.
• Solution also validated using a 3rd party test suite.

Engagement Model: A Team of 11 people for more than 4 years (on going) in ODC with T & M.

5. Mapping 3rd party synthesized Netlist to tool's native Netlist

The Customer: Customer is a leader in emulation solutions for hardware verification and hardware-software co-verification. Its solutions are used by most of the leading semiconductor companies to verify their SOC's.

The Application: It's an HDL compiler for hardware emulation & hardware-software co-simulation.

Mirafra's responsibility:

• Integration with the 3rd party synthesis tool (Concorde) provided a netlist that was mapped to the tool's native netlist which was then directly provided to its backend.
• Concentrated effort to map the memory macro modules.
• Solution validated using the customer's entire regression test suite.

Engagement Model: A Team of 11 people for more than 4 years (on going) in ODC with T & M.

6. Several key validation projects

The Customer: Customer is a leader in emulation solutions for hardware verification and hardware-software co-verification. Its solutions are used by most of the leading semiconductor companies to verify their SOC's.

The Application: It's an HDL compiler for hardware emulation & hardware-software co-simulation

Mirafra's responsibility:

• Several key validation projects undertaken and executed: this includes writing the test plan, developing a new testsuite (or harnessing an existing test suite), and validating the software using the same.
• Validation of DesignWare models
• Development and validation of Behavioral constructs & Four-state test suites
• Validation of optimizations for long chain of muxes into a balanced tree.
• Validation of Accelerated test benches.
• Validation of SV – DPI based transactors support
• Validation of System Verilog & Mixed-HDL support
• Validation of “Fast Synthesis” flow (a new methodology that provided faster synthesis in customer's tool flow).

Engagement Model: A Team of 11 people for more than 4 years (on going) in ODC with T & M.

7. Management of the entire nightly Regression System

The Customer: Customer is a leader in emulation solutions for hardware verification and hardware-software co-verification. Its solutions are used by most of the leading semiconductor companies to verify their SOC's.

The Application: It's an HDL compiler for hardware emulation & hardware-software co-simulation.

Mirafra's responsibility:

• Development of new & enhancement of existing scripts to manage the entire regression system.
• Checkout & compilation of build followed by a run of the entire regression suite comprising of more than 16000 regressions every night.
• Results posted in an orderly manner on the internal webpage on a daily basis.
• All failures analyzed and culprit analysis done for each of them.
• Multiple software streams handled at the same time during releases.

Engagement Model: A Team of 11 people for more than 4 years (on going) in ODC with T & M.

8. Simulation Kernel for Verilog

The Customer: Customer is an EDA software company that is pioneering an intelligent verification technology which utilizes design insight to enable rapid verification closure while leveraging existing methodology infrastructure.

The Application: The customer had a simulator that was 50-100 times slower than the industry standard simulators in the market. Mirafra was engaged to deliver 10-20 times performance improvement on this.

Mirafra's responsibility:

• Mirafra Technologies evaluated the customer needs and its current simulator architecture and defined a set of projects to improve the performance.
• This process required senior Mirafra engineers to interact with the technical leaders in the customers' engineering team and get a buy in for the various projects.
• One of the key projects was to implement the kernel as a byte-code engine.
• Mirafra owned the complete project from architecture to validation.
• The components developed were - byte code compiler, value storage infrastructure, and fast byte code interpreter using gcc extended labels.
• As a result of these projects the customer saw 10-20 times improvement in simulation times.
• Mirafra ensured that the implementation was completely backward compatible and passed the extensive set of tests that the customer had.
  

Engagement Model: A Team of 3 people for more than 1 year in ODC with T & M.

9. Spectre to Spice Simulator

The Customer: Customer is the first and only company to develop SPICE entirely based on current instead of voltage, which has significant advantages in performance, accuracy and capacity over traditional SPICE, particularly as integrated circuit geometries shrink and leakage currents grow.

The Application: The customer's simulator supported Spice as the input language. One of his customers wanted the simulator to accept Spectre language.

Mirafra's responsibility:

• Along with senior technical personnel from the customer Mirafra engineers defined a translator from Spectre to Spice.
• The translator was implemented in C++ with many components of the compiler written from scratch. These included lexer, recursive descent parser and a two pass translator.
• Extensive error checking was implemented as part of the parser. Also great care had to be taken to keep the translation close to the original to aid in understanding.
• A test suite of nearly 1000 testcases was developed to test and maintain this software.
• The software had to be incrementally enhanced over the lifetime of the project based on customer requirements.

Engagement Model: A Team of 3 people for more than 2 years (on going) in ODC with T & M.

10. VCD Parser and Power Report Generation

The Customer: Our customer is developing EDA tool solutions to address all aspects of both dynamic and leakage power in semiconductor designs.

The Application: The customer needed a solution to generate power reports from the value change dumps (VCD) of a design. In addition, the tool needed to estimate the amount of power that the transformations applied by the customer tool would save.

Mirafra's responsibility:

• Mirafra engineers designed and implemented a VCD parser component and set of applications around it to solve the problem.
• The implementation was done in around 7000 lines of C++ and few hundred lines of Perl code.
• The solution generates a set of very user friendly reports that are utilized by the tool and the end customers.
• Mirafra also developed a comprehensive set of tests to validate and maintain this solution.
• The solution was delivered to end customers and forms an integral part of the customer toolset.

Engagement Model: A Team of 3 people for more than a year (on going) in ODC with T & M.