Mirafra has successfully executed multiple projects in Design & Verification for three market leaders in areas of telecom, networking & communication.

Mirafra has worked extensively on 3G Modem IP with applications in high-end smart phones, L2/L3 Switches targeting SMB, L2 managed and L3 stackable sockets, Single Chip Solution for voice-over-wireless LAN enabled handsets, Low Power DDR2 & LCD Controllers for CDMA mobile application, USB Subsystem s, XDR memory and PCI Express IP.

Mirafra has used its expertise in advanced verification techniques to deliver fourteen successful designs with zero bug quality

1. Verification of a Storage Area Network SOC

The Customer : Customer is a world leader of enterprise-class products that intelligently connect storage, servers and networks.

The Application: It is a multi-million gate storage processor chip which supports multiple protocols and had applications in intelligent storage I/O, server clustering, high performance data networking and intelligent storage platform solutions, including storage virtualization. It is a complex chip with 15 different blocks, 7 processors at 350 MHz, with multiple clock domains.

Mirafra's responsibility:

• Part of full chip Verification of SOC.
• Complete ownership of Functional Verification Of 5 Blocks of SOC
• A data path block with one ARC processor, SSRAM controller, DDR2 controller interface,
• PCIe block, peripherals like Ethernet, JTAG etc.
• A buffer queue manager block
• PCIe, PCS, CMAC blocks.
• Proposed and developed verification environment from scratch. The environment was architected based on RVM methodology and designed to be reusable at gate level simulations and block level environments.
• Developed verification plan and defined verification closure criteria based on functional coverage and code coverage. Developed comprehensive test plans.
• The environment and all test benches were developed in Vera HVL. All test benches were self checking. Except for few directed test cases, stimulus generated using constraint randomization.
• Created detailed documentation for the environment, test benches and reported bugs.

Engagement Model:

A team of 8 people for 9 months on site based on Turnkey with fixed cost.

2. Verification of Wireless 3G Modem IP

The Customer : Customer is a major mobile maker .

The Application: 3G Modem IP with applications in high-end smart phones.

Mirafra's responsibility:

Defined Verification Strategy using multiple verification techniques. These included Constrained Random Verification, Formal Verification and C/VHDL based verification. Defined verification plan and sign-off criteria.

Architected, designed and developed VMM based methodology for full IP verification using System Verilog. The environment was designed to be usable with and without ARM processors in DUT. Designed to be capable of measuring coverage and other sign-off metrics. Test cases were developed and analyzed. Driven verification to closure by achieving desired sign-off metrics.

Identified features suitable for formal verification. Defined formal properties and used IFV to verify the correctness. Converted PSL based formal properties into SV assertions for dynamic simulation coverage.

C/VHDL based verification test-bench is chosen to provide sanity test harness to the licensees of the IP to check the integration into their design.

Engagement Model: A team of 15 people for 12 months onsite based on T&M (Time & Material).

3. Design & Verification of WCDMA Sub Module

The Customer : Customer is a major mobile maker .

The Application: 3G Modem IP with applications in high-end smart phones.

Mirafra's responsibility:

• Design interconnects between various sub modules based on OCP2 specification
• Development of test plan for top level and module level
• Development and analysis of test cases.
• Achieving desired sign-off metrics based in coverage.

Engagement Model: A team of 2 people for 6 months onsite based on T&M (Time & Material).

4. Verification of Low Power DDR2 Controller & LCD Controller

The Customer : Customer is a world leader of wireless and CDMA technologies.

Mirafra's responsibility:

• Development of Verification Environment, Test plans, Coverage plans.
• Development and Analysis of Test cases
• Implementation and analysis of functional coverage and assertion coverage.
• Achieving desired sign-off metrics.
• Creating detailed documentation

Engagement Model: A team of 2 people for 4 months onsite based on T&M (Time & Material)

5. Verification of L2/L3 Switch

The Customer : Customer is a world leader in communication solutions for voice, video, data and multi media in wired and mobile environment.

Application : L2/L3 switches targeting SMB, L2 managed and L3 stackable sockets. Equipped with QSGMII/SGMII interfaces, the device would be able to sustain 72 Gbps full duplex bandwidth.

Mirafra's responsibility:

• Development of test plan for new features.
• Development of new test cases and porting of old test cases from previous revisions.
• Implementation of functional coverage and assertions.
• Analysis of test cases and functional coverage.
• Achieving desired sign-off metrics.
• Creating detailed documentation

Engagement Model : A team of 2 people for 4 months onsite based on T&M (Time & Material).

6. Verification of Wireless LAN SOC

The Customer : Customer is a leading provider of solutions that enable VOIP, VoWi-Fi and FMC on Handsets, IP Phones, ATAs, Residential Gateways, Game consoles and PDAs.

The Application: Single chip solution for voice-over-wireless LAN enabled handsets. The system has an ARM processor with AHB, APB buses, WLAN (Mac & Phy), SDRAM, LCD, DMA controller, USB and other peripherals etc.

Mirafra's responsibility:

• Developed verification environment in System Verilog using VMM methodology.
• Defined test plan and functional coverage plans. Implemented test cases and coverage points.
• Analyzed test cases and coverage results. Driven the verification to closure with desired quality.
• Created detailed documentation for the environment, test cases, coverage points and bugs.
• Gate level simulation setup for sign-off.
• Test Vector generation for Test Chip.

Engagement Model : A team of 4 people for 12 months onsite based on T&M (Time & Material).

7. Verification of USB Subsystem

The Customer : Customer is leading mobile platform maker and DSPs.

The Application: USB Subsystem suitable for digital camera application SOCs. Chip included OHCI (USB1.1 Host), EHCI (USB2.0 Host) and High speed device controller (USB2.0 device) with multiple USB ports such as advanced ULPI and legacy DP/DM interfaces.

Mirafra's responsibility:

• Developed verification environment, defined test plan and functional coverage plan.
• Developed and analyzed test cases, assertions and coverage points.
• Driven the verification to closure by achieving desired sign-off metrics.
• Created detailed documentation for the environment, test cases, coverage points and bugs.

Engagement Model : A team of 4 people for 12 months in ODC with T & M (Time and Material).

8. Verification of XDR and DDR2 Memory Controllers

The Customer : Customer is a leading provider of high performance interface solutions enabling high performance in video game consoles, digital TVs, set-top boxes, network switches and routers.

The Application: XDR memory architecture achieves an order of magnitude higher performance than today's standard memories while utilizing the fewest ICs.

Mirafra's responsibility:

• Defined environment architecture and verification plan. Verification closure was based on functional coverage.
• Developed the environment in System Verilog. Defined functional coverage and implemented coverage points.
• Developed and analyzed test cases. Achieved desired closure criteria.

Engagement Model : A team of 2 people for 4 months onsite based on T&M (Time & Material).

9. Verification of PCI Express IP

The Customer: Customer is a leading provider of high performance interface solutions enabling high performance in video game consoles, digital TVs, set-top boxes, network switches and routers.

The Application: PCI Express IP

Mirafra's responsibility:

• Owned and implemented Specman/e based verification environment for PCIe Data link and MAC layers.
• Responsibilities included definition of TB architecture, definition of feature list and coverage points and corresponding implementation and closure of the same.

Engagement Model : A team of 2 people for 4 months onsite based on T&M (Time & Material).

10. Verification of FlexRay IP

The Customer : Customer is a leader in programmable logic solutions with over 50% market share.

The Application: PCI Express IP with application in automobile industry.

Mirafra's responsibility:

• Responsibilities included definition of TB architecture, definition of feature list and coverage points and corresponding implementation and closure of the same.

Engagement Model : A team of 1 people for 4 months onsite based on T&M (Time & Material).